Jitter measurements for CLK generators or synthesizers - AN2744

Clock (CLK) generators and synthesizers form the pulse of a complex digital system and errors in a clock's signal quality can have wide-ranging effect. One of the most important performance measurements is clock jitter. Jitter is defined as "the short-term variation of a signal with respect to its ideal position in time." In a clock generator chip, there are many factors which contribute to output clock jitter, such as the device noise, supply variation, jitter in the reference clock, loading condition, and interference coupled from nearby circuitry. Jitter can be measured in different ways, including period jitter JPER, cycle-to-cycle jitter JCC, and accumulated jitter JACC. In general, jitter consists of the deterministic jitter and random jitter. Since the deterministic jitter in most digital systems is introduced frommany different bit patterns from the digital data, clock signal jitter can usually be considered to be just random jitter. In this application note, we will go over the definitions and introduce test setups for making measurements. Jitter definitions Period jitter: JPER Jitter JPER is the most popular jitter measure. It is the time difference between a measured cycle period and the ideal cycle period. Due to its random nature, this jitter can be measured as Peak-to-Peak or by Root Mean Square (RMS). Let's define the clock rising edge crossing point at the threshold VTH as TPER(n), where n is the time domain index, as shown in Figure 1. Mathematically, we can describe JPER as where T0 is the ideal clock cycle. Figure 1 shows the relation between JPER and TPER in a clock waveform. Figure 1. Period Jitter Measurement. Cycle to cycle jitter: Jcc Jitter Jcc is the time difference of two adjacent clock periods. This is also called "Short Term Jitter." It depends only on the adjacent clock cycles. For some digital circuits, Jcc is more meaningful than JPER. Jcc is the right parameter for calculating the margins for set-up time and hold-on time. If only JPER is employed in the calculation, the result is often too conservative. As an extreme example, to a spread spectrum (SS) clock, Jcc can be relatively small, but its JPER can be very large when the measuring time is comparable to Page 1 of 4 the spreading period. Jcc is measured by its Peak-to-Peak value in a given time period. It is mathematically defined as where n is a cycle index and N is a number for a given period. Figure 2 shows the relation between Jcc and TPER(n) in a clock waveform. Figure 2. Cycle-to-Cycle Jitter Measurement. Accumulated jitter: JAC(n) Jitter JAC(n) is the time displacement of the edges of a clock relative to the triggering edge of the same clock. This jitter is a function of n and it is the general case of JPER. It is measured by its Peak-to-Peak value or RMS. It gives the maximum discrepancy between two clock rising edges n cycles apart. For a digital system with synchronized packet data, this jitter measure may be the right one for system timing analysis. Its mathematic form is given as It is noted that JAC(n) is dependent on the cycle index n. Figure 3 depicts how to measure JAC(n) from a clock signal. Figure 3. Accumulated jitter measurement. Jitter measurement Time domain jitter measurement A high precision digital oscilloscope is commonly used to measure jitter. When the clock jitter is 10 times or larger than the triggering jitter of the oscilloscope, the clock jitter can be measured by triggering at a rising edge of the clock signal and measuring the jitter at the next rising edge. SEMI (Semiconductor Equipment and Materials International) [1] has specified a more accurate method for measuring the period jitter of high-speed clock. As shown Figure 4, the trigger is generated by the clock to be tested. This eliminates the internal jitter due to the clock source in digital oscilloscope.